An Approach for Syntax Tree Construction using Formal Specification Language

A Compiler is a language translator which translates high level language to low level language, this is the task of a compiler. Removing the bugs of source program does not assure that the generated target code is completely error free because there may be bugs in compiler also. So it is more important to verify the Compiler itself. Lexical analyzer is a first phase and main part of compiler used for scanning input stream of characters and grouping into tokens. In this paper formal construction of syntax tree is described from the regular expression to verify the lexical analyzer and this is the aim of paper. If the syntax tree will be constructed successfully for the given regular expression then the lexical analyzer will be verifi ed. Formal specifications can be rigorously validated and verified leading to the early detection of specification errors. The widely used formal specification language is VDM(Vienna Development Method), Z notation and B. Here t he specification is described using Model oriented formal specification languages Vienna Development Method (VDM) because Vienna Development Method provide support for concurrency control and also using VDM Software requirement specification can be automatically converted into computer source code. Z notation does not support for concurrency control and also software requirement specification can not be automatically converted into computer source code. B method also does not support for concurrency control. Keywords—Compiler Verification, Formal Specification, Lexical Analyzer, Regular Expression, VDM.